The present invention relates to a cache memory apparatus, a cache control method, and a microprocessor system, and especially to a cache memory apparatus, a cache control method, and a microprocessor system that are capable of efficiently caching an instruction code.
In recent years, incorporation of various functions and higher performance are demanded for electronic devices represented by AV equipments and home appliances. Therefore, higher performance is also demanded for a microprocessor system that controls these electronic devices. In general, the microprocessor system uses a prefetch buffer and a cache memory apparatus for preventing performance degradation at the time of fetching an instruction code from a low-speed memory.
The prefetch buffer can previously store instruction codes after an address of a currently executed instruction to a flip-flop and the like. This prevents the performance degradation that is caused by slow reading speed of the memory when reading the instruction code from the memory at the time of executing a normal instruction. The cache memory apparatus can previously store frequently used instruction codes to RAM (Random Access Memory). This prevents the performance degradation that is caused by slow reading speed of the memory at the time of reading the instruction code from the memory mainly upon a branch into a subroutine.
The larger the size of the prefetch buffer and the memory in the cache memory apparatus, the more instruction codes they can store in advance. Accordingly, the size of the memory must be larger in order to more reliably prevent the performance degradation that is caused by the slow reading speed of the memory. However, a larger size of the prefetch buffer and the memory in the cache memory apparatus increases the chip area, thereby increasing the manufacturing cost. Thus, trading-off between the performance and the cost must be taken into consideration to select a capacity with a minimum memory size that can produce a maximum advantage for these memory sizes.
Japanese Unexamined Patent Application Publication No. 9-305490 discloses a technique regarding a microprocessor system that can prevent a capacity conflict from being generated and the performance of the instruction cache from being negated. FIG. 9 is a block diagram for explaining the microprocessor system disclosed in Japanese Unexamined Patent Application Publication No. 9-305490. A microprocessor system shown in FIG. 9 includes a CPU 101, an instruction cache 102, an address bus 103, a data bus 104, and a counter 105.
The counter 105 receives a cache access notification signal S1 and a branch generation notification signal S2 that are output from the CPU 101 and outputs a cache function stop signal S3 to the instruction cache 102. The CPU 101 generates the cache access notification signal S1 for each access to the instruction cache 102. Therefore, a value of the counter 105 is decremented every time the CPU 101 accesses the instruction cache 102. Moreover, the CPU 101 generates the branch generation notification signal S2 for every subroutine call or every time when a branch into a minus direction is established. The counter 105 is initialized when the branch generation notification signal S2 is supplied, and the value of the counter 105 will be the number of entries. Further, when the value of the counter 105 is zero, the counter 105 outputs the cache function stop signal S3 to the instruction cache 102 to stop the function of the instruction cache 102.
Next, an operation of the microprocessor system shown in FIG. 9 is explained. FIG. 11 shows transitions of the instructions cached in the instruction cache 102 when a program shown in FIG. 10 is executed. In a loop of the program shown in FIG. 10, the CPU 101 sequentially fetches instructions A, B, C, and D from a main memory (not shown) and loads the instructions A, B, C, and D in the instruction cache 102 while executing the instructions A, B, C, and D (steps 201, 202, 203, and 204). In each of the steps 201, 202, 203, and 204, as the CPU 101 generates the cache access notification signal S1, the value of the counter 105 is decremented like 3, 2, 1, and 0. Consequently, all the entries of the instruction cache 102 are occupied, and after that, the entries in the instruction cache 102 will not be replaced by the generation of the cache function stop signal S3 in the counter 105.
Next, the CPU 101 sequentially fetches instructions E, F, G, and H from the main memory and executes the instructions E, F, G, and H (steps 205, 206, 207, and 208). In this case, since the entries in the cache 102 will not be replaced, the instructions A, B, C, and D remain in the instruction cache 102.
Next, after an instruction H, which is a branch instruction, is executed, the instruction A is executed again. In this case, the instruction A is already loaded into the instruction cache 102. Thus, there will be a so-called cache hit (step 209). Subsequently, also when the CPU 101 executes the instructions B, C, and D, as the instructions B, C, and D are loaded into the instruction cache 102, there will be a cache hit.
As described above, in the microprocessor system disclosed in Japanese Unexamined Patent Application Publication No. 9-305490, at the time of executing the program including the loop, it is possible to improve the performance of the instruction cache by disabling the cache function when the instruction cache is occupied.